In data processing systems as, for example, digital computer systems which handle binary data information, the data and control information used therein is contained in data words which normally comprise a fixed number of binary data bits. Preferably, in most computer systems such data words are comprised of data bits combined in multiples of four, i.e., data and control words using 4 bits, 8 bits, 12 bits, 16 bits, etc.
Often such data words are utilized with peripheral and terminal equipment associated with the data processing system which is configured, for example, for human control and interaction and frequently has value generating elements which do not necessarily require the same modulus (i.e., the same total number of data bits) as that used by the data processing system. Such lack of correspondence between the number of data bits utilized in the data words of the data processing system and the number of data bits utilized for generating the desired information in the associated equipment results in an inefficient use of the system components and/or the requirement for additional circuitry which duplicates the value generating elements and operates in parallel with them but on a modulus which is more consistent with other system requirements. Such conventional methods for dealing with a lack of correspondence between the data processing system and the assocated equipment often tend to increase the cost, complexity and power consumption of the overall system while at the same time decreasing the reliability thereof and occasionally introducing a failure mode from which the device is unable to recover.
It is desirable, therefore, to devise a system for permitting an optimum utilization of existing system components so as to reduce the inefficiencies, costs and complexities involved in such lack of correspondence, which system would be integral with the overall data processing apparatus and not require redundant components.
In a specific application, for example, such a system can provide optimum utilization of addressable memory elements where the address word is composed of more than one sub-word, for example, and each of such sub-words do not require all possible combinations of its binary bits in order to convey all of the data information needed. If the sum of the bits of the sub-words is more than the number of bits necessary to address an addressable memory element, for example, the system of the invention can provide an appropriate compression of the sub-word data information so as to produce an address word which has fewer bits than the total number of bits in the sub-words.